[2026 Campus] Engineer / Senior Engineer (Design Verification)

Job Description[What you will do]
• Module/IP/SOC design verification.
• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization-based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, System Verilog, Verilog and SystemC.
• Low Power verification.
• Formal verification.
• Verification automation flow.

#LI-WC1Requirement[What you will bring]
• Bachelor's Degree (with min.

2 years of relevant experience) /Master's Degree in EEE/Computer/IC design.
• IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong Experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Python, Perl, makefile Cshell.
• Quick to learn new technology.

Location: One North, Singapore

[About the Team]
ASIC DV Team focus on developing full and advanced verification methodology IP/SOC.

You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking.

A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.



In MediaTek, we promote diversity and inclusiveness.

Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!