Overview
This role leads the process engineering function for a 12” wafer bumping fabrication line, overseeing end-to-end operations from photolithography to reflow.
The position focuses on yield optimization, process innovation, and technical excellence while managing a large multidisciplinary engineering team to support high-volume manufacturing and advanced wafer-level packaging development.
Responsibilities
- Lead and manage the overall 12” bumping process engineering organization.
- Drive yield, quality, and process capability improvement across multiple modules.
- Oversee new product introductions and technology transfers to production.
- Implement robust process control systems (SPC, DOE, FMEA, FDC) and promote data-driven manufacturing.
- Foster engineering talent development, team performance, and safety compliance.
- Collaborate with cross-functional teams to ensure fab stability, efficiency, and customer satisfaction.
Qualifications
- Bachelor’s or Master’s in Microelectronics, Material Science, Chemical, or Electrical Engineering.
- 12–18 years of semiconductor process experience, including at least 5 years in leadership roles in 12 wafer environment .
- Proven expertise in wafer bumping or WLP processes (UBM, RDL, Cu pillar, solder bump, or WLCSP) .
- Strong track record in yield improvement, process integration, and technology development.
- Hands-on experience with major fab equipment (TEL, ASML, EVG, DISCO, SUSS) .
- Skilled in SPC, DOE, FMEA, and data analytics tools (e.g., JMP, Spotfire, Tableau) .
If you would like to be considered for this opportunity, please forward a copy of your full CV to
Data provided is for recruitment purposes only.
Only shortlisted candidates will be notified.
Business Registration Number: D | Licence Number: 10C5117 | EA Registration Number: R
Application notes
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