DFT Engineer

Job Description:

1. Participate in the architecture and implementation of DFT (Design-For-Test) features for SoC/IP, including scan chain design, ATPG, pattern generation, simulation, and diagnosis;
2. Perform CP (wafer-level) and FT (final test) yield analysis based on diagnosis results;
3. Research and evaluate state-of-the-art DFT architectures and methodologies for SoC/IP designs;
4. Develop and maintain in-house DFT flows and automation methods, and deploy them across multiple projects;
5. Troubleshoot DFT-related issues during design implementation and silicon bring-up phases.
   
   

Requirements:

1. Master's degree or above in Computer Engineering, Electrical Engineering, or a related field;
2. 3–5+ years of working experience in ASIC/SoC development;
3. Solid understanding of Verilog and familiarity with front-end design flow;
4. Knowledge of DFT concepts and techniques, including scan insertion, MBIST, and boundary scan;
5. Proficient in using industry-standard tools such as Synopsys Design Compiler, DFT Compiler, TetraMAX, VCS, or Mentor Tessent;
6. Experience with ATPG, MBIST, or diagnosis; experience in yield analysis is a strong plus;
7. Skilled in scripting with Makefile, Tcl, Perl, or Python for design automation;
8. Strong communication and presentation skills in English, with a passion for test methodologies and innovation.