Responsibilities
Define verification plans and test cases based on chip design specifications, and establish the verification environment
Collaborate with chip design engineers in identifying and fixing design defects and continuously improve verification coverage
Participate in gate-level simulation and formal verification
Optimize tools and the verification environment to enhance verification efficiency
Job Requirements
Bachelor's degree or above in Electrical Engineering, Computer Engineering, Computer Science, or related fields
Familiar with Verilog, C, SystemVerilog, UVM
Familiar with scripting languages such as Perl, Shell, and/or Tcl
Seniority level
Entry level
Employment type
Full-time
Industry
Semiconductor Manufacturing
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