Job Opportunity
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In this challenging position, the individual will be responsible for thoroughly understanding digital design specifications of various IP blocks and SoC architecture definition.
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>- Develop detailed module level and SoC level test plans for all functional features based on design specs.
>- Develop ASIC verification environment including stimulus, checkers, assertions, monitors, and scoreboards.
>- Develop directed and constrain-random verification functional tests, and simulate using EDA tools to verify functional blocks are working.
>- Execute verification plans, including design bring-up, DV bring-up, regression enabling for all features.
>- Collaborate with design teams to debug functional test cases and deliver functionally correct designs.
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The ideal candidate must have a proven ability to achieve results in a fast-moving, dynamic environment.
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Requirements
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>- BSEE or MSEE, entry-level.
>- Strong communication, analytical, and documentation skills, and ability to interface with other groups.
>- Strong VLSI/ASIC functional verification experience, preferably with exposure to complex, high-speed custom VLSI/ASIC products.
>- Strong hardware functional verification language and object-oriented language development skills.
Preferably with SystemVerilog/UVM experience.
>- Familiar with ASIC verification methodology, EDA tools, and development flow.
>- Working experience or familiarity with Ethernet L2/L3 switch/router, high-speed IO (USB-2/3/4, PCIe gen 2/3/4/5, MIPI CSI-2/DSI-2, and SATA), Flash controller, or CPU peripherals, AMBA bus, and SoC system controller.
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