Engineer, Yield Analysis, NTI

Job description

Our vision is to transform how the world uses information to enrich life for all.

Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners.

The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible.

We do it all while committing to integrity, sustainability, and giving back to our communities.

Because doing so can fuel the very innovation we are pursuing.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our vision is to transform how the world uses information to enrich life for all.

We have an opening for Yield Analysis Engineer for NAND Technology Deparatment in Singapore.

We are looking for candidate that is passionate to innovate in data analytics, and curious to ask what, how and why?

In this role you will be responsible for providing key feedback and direction on yield improvement activity for NAND memory technology! This role requires a high degree of collaboration across virtually all company functions, up to and including the Executive level.

As Yield Analysis Engineer , you will be responsible for developing innovative NAND product technologies, define, and execute various effective actions to enable solutions to improve yield, quality, reliability, and hit key milestones & achieve the required performance within committed timelines.

Your responsibilities will include, but are not limited to, the following:

Discover yield issues in NAND development and identify unique metric or combination of metrics, such as wafer/dice/tile shading, ECATS or other custom metric for issues quantification.

Interact with process area, process integration, yield, failure analysis, product engineering, design, and layout teams to drive clear definition of yield, cell, CMOS, qual, and reliability issues and pareto and derive improvement actions needed across tech-nodes and designs.

Own and drive non-standard deep dive statistical analysis of inline, probe, cell, and other critical metrics to define issues/problems, enable early inline detection, and improve the product yield and quality.

Quantify and track progress on the issue hit hate, line impact, gap to program goal.

Quantify yield improvement/downside seen based on process/probe changes.

Initiate data mining and correlation study on new issue seen.

Initiate PFA request to identify root cause of yield issue.

Perform inline correlation study to establish inline prediction to yield issue.

Make yield projections based on expected improvement/downside.

Conduct yield trend analysis, identify root causes in process step, conversion, algorithm change, and design, for yield shift.

Continuously develop/re-define inline detection in collaboration with metrology and RDA team.

Identify and define gaps with current test and co-develop (with product, probe, param engineering) unique parametric/probe bins to detect new fail modes as well as validate new program release.

Collaborate with module owners to identify, quantify key module deficiencies/technology gaps, and drive cross-functional teams to address.

Optimize existing layout, conceptualize, and develop innovative solutions to meet product requirements and manufacturability.

Develop and innovate techniques in extracting data from different databases through various query languages and automate through scripting to improve work efficiency.

Assist and support the transfer documentation of layout/architecture fundamentals of new technology from R&D to manufacturing fab.

Successful candidates for this position will have:

Experience in the semiconductor industry in the area of Yield Analysis.

Prior experience with monitoring trends and root causing trend variation to process variations and being able to build paretos.

Exposure to edge of wafer analysis to help improve the yield of full wafer is desirable.

Prior understanding of building dashboards to capture line to probe outputs is additional plus.

Ability to develop a strong holistic end to end understanding of PI module on new NAND technologies and related structural & electrical fail mechanisms.

In-depth knowledge and direct experience with nonvolatile memories along with good understanding of the process flow, interaction of process & device, common yield & reliability issues are desirable.

Exposure to R&D and transfer/manufacturing is desirable.

Deep understanding of probe failure mechanism, ability to do electrical bench data collection is desirable.

Ability to be self-motivated and self-governing with proven ability to work in a demanding and dynamic environment.

Ability to drive and coordinate cross-functional teams to achieve various goals.

Solid analysis, communication and reporting abilities with demonstrated presentation abilities.

Ability to travel for extended periods of time to the US or other fabs for collaborative R&D work.

Education:

Bachelors in Electrical/Electronics Engineering, Communication Engineering.

Required Skill Profession

Computer Occupations