Key Responsibilities:
- Develop and implement comprehensive verification plans for IP and SoC levels.
- Architect and build reusable testbenches and verification environments using UVM (Universal Verification Methodology).
- Create directed and constrained-random tests to identify design bugs.
- Develop functional coverage and assertion checks to ensure verification completeness.
- Analyze simulation results, debug test failures, and work with design teams to resolve issues.
- Automate verification flows and regressions using scripting languages.
- Support emulation and FPGA prototyping efforts.
Qualifications and Skills:
- Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Science, or a related field.
- Solid experience in functional verification of ASICs/SoCs.
- Strong proficiency in SystemVerilog and UVM methodology.
- Experience with verification tools and simulators (e.g., VCS, Xcelium, Questa).
- Programming and scripting skills (e.g., C/C++, Python, Perl, TCL) are highly desirable.
- Knowledge of formal verification techniques is a plus.
- Strong analytical and debug skills with a keen attention to detail.
- Ability to work effectively in a collaborative, cross-functional team.