Integrated Circuit Designer

JD:

• Execute all tasks assigned to a Middle-End engineer:
• Prepare clean and optimized gate-level netlists
• Develop and validate the design constraints (SDC)
• Support Design for Test (DFT) requirements
• Conduct formal equivalence checking
• Support definition and validation of power intent using UPF
• Provide inputs to support floorplanning activity
• Assist in defining and validating the Clock Tree architecture
• Perform Static Timing Analysis (STA) at pre- and post-layout stages
• Implement and validate ECOs
• Drive and contribute to the continuous improvement of middle-end
  implementation flows and methodologies

Requirements:

• Bachelor or Master in Electrical/Electronic Engineering
• 7+ years of experience in digital IC design
• Proficient in using industry-standard EDA tools (Synopsys, Cadence)
• Strong communication skills for effective collaboration with front-end and back-end design teams
• Excellent analytical skills for identifying and resolving design issues
• Knowledge and working experience with graphics processor