RightSilicon Technology is a Singapore registered company which provides ASIC design services and turn-key manufacturing services, including specification design, SOC design, IP, physical design, post simulation, post varication, packaging design, testing and logistics.
Responsibilities
Generate IP design kit with components listed, but not limited to, below:
Various format of liberty (NLDM, CCS, ECSM and LVF)
- Verilog behavior model
- Synthesizable RTL model
- LEF/Milkway view
- EMIR views
- DFT views
Perform QA check on DK components listed, but not limited to, below:
Spice to liberty correlation
- Liberty syntax and trend check
- Spice to Verilog equivalence check
- Verilog coverage check
- Component in-view and cross-view check
- Integration test cases
- Support scripting for various tasks in the design kit generation
- Standard cell library liberty characterization
Participate in various phase of circuit design of IP and SOC
Schematic design
- Floorplan and layout supervision
- Post-layout simulation
- EMIR analysis
- Documentation
- Silicon validation support
Requirements
- Bachelor and above degree with EE or Engineering related
- Minimum 3 years of IP design kit experience
- Familiar with various liberty file formats.
Have hand-on experience with Synopsys Siliconsmart/Cadence Liberate - Familiar with IP integration on SoC
- Familiar with IP Design Kit QA software like Qualib/Solido IP validation suite
- Excellent scripting capability and familiar with Linux shell script, verilog and tcl/perl
- Hand-on experience on digital RTL to gds design flow with various EDA tools
- Good foundation on transistor-level CMOS circuit design.
Experience on designing emerging memory(MRAM/RRAM/PSM), non-volatile memory (flash/EEPROM/OTP), SRAM, LDO, DC-DC converter and other analog blocks is a plus - Good documentation and communication skills, teamwork spirit
- Active working attitude with self-motivation
- Fluency in English and Mandarin to liaise with Mandarin speaking clients