Job Summary
We are looking for a skilled Layout Design Manager to join our semiconductor design team in Singapore.
You will be responsible for performing full-custom IC layout design, physical verification, and layout optimization for advanced FinFET technology nodes.
This role involves close collaboration with circuit design engineers to deliver high-performance and reliable chip layouts.
Job Responsibilities
- Perform IC layout design based on integrated circuit schematics.
- Plan and develop layout floorplans; collaborate with circuit design engineers to optimize layout for best circuit performance.
- Conduct physical verification including DRC, LVS, ERC, and Self-heating/EM checks.
Requirements
- Proficient in full-custom layout design flow, including physical verification, parameter extraction, and DFM requirements.
- Relevant experience in IC design and verification.
- Hands-on experience with FinFET layout design, and familiarity with FinFET self-heating layout process.
- Skilled in using EDA tools such as Cadence, Synopsys, StarRC, and DRC/LVS verification tools.
- Strong knowledge of wafer-on-wafer process layout.
- Excellent learning ability, good communication skills, and a strong team player.