Logic Verification Engineer

Responsibilities:

• Perform chip verification for new product development.
  
  
• Participate in IP- and system-level simulation verification.
  
  
• Develop and maintain UVM-based verification environments according to architectural documentation.
  
  
• Define and achieve functional coverage targets; improve code and functional coverage based on the verification plan.
  
  
• Execute verification across gate-level and post-simulation stages; debug issues, resolve cases, and ensure verification tasks are completed at each project milestone.
  
  
• Support validation requirements and contribute to successful tape-out.
  
  

Qualifications:

• M.S. in Electrical Engineering, Microelectronics, or related field.
  
  
• 5+ years of experience in Pre-Silicon verification.
  
  
• Solid knowledge of UVM methodology (strong advantage).
  
  
• Proficiency in Verilog/System Verilog.
  
  
• Strong scripting skills in at least one language: Python, Perl, Tcl, or Shell (required).
  
  
• Experience with chip CP/FT test preferred.
  
  
• Leadership or management experience is a plus.