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Urgent! Senior Engineer – HIG PSE IE – Wafer Reliability Operation Job Opening In Singapore, Singapore – Now Hiring Micron
Our vision is to transform how the world uses information to enrich life for all.
Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners.
The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible.
We do it all while committing to integrity, sustainability, and giving back to our communities.
Because doing so can fuel the very innovation we are pursuing.
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a HIG PSE IE for Wafer Reliability Ops, you will lead Wafer Reliability Scheduling and drive the weekly triage meetings between Probe Operations and the Site IE Planning team.
This role is critical to ensuring seamless coordination across engineering, manufacturing, and planning functions to support timely and efficient wafer reliability testing.
Key Responsibilities
Weekly Triage Leadership
Facilitate and lead weekly triage meetings with Probe Operations and Site IE Planning to align on:
Tester availability
Probe card readiness
Wafer allocation and production planning
Turn-Around-Time (TAT) compliance and issue resolution
Wafer Reliability Scheduling
Develop and maintain wafer loading plans based on forecast and site capacity.
Coordinate with flex cap and probe card teams using IE modeling tools.
Execute tactical planning for wafer shipments across sites based on multiple lots execution strategies
Capacity & Resource Planning
Collaborate with NPI, MH, and PE teams to consolidate HBM roadmap requirements.
Build and manage capacity loading plans and dashboards for pre-qual NPI execution
Monitor tester and probe card activity, ensuring that usage is recorded and MOR capacity is planned effectively for reporting needs.
Process & System Coordination
Translate engineering requests into executable test flows in MAM/MES systems.
Ensure compliance with RAS audits and QA standards.
Support debug system setup and operation for ELFR and Rel Ops
Cross-Functional Collaboration
Liaise with Fab, IE Planning, and Media Health teams to ensure alignment on wafer-level engineering cycles of learning.
Drive forlot staging analysis, and sampling plan execution
HIG team member should do him/ her best to demonstrate Micron values in his/ her job performance.
People: We care about each other
Innovation: We develop solutions that shape the world’s future
Tenacity: Nothing shales our resolve
Collaboration: We work as one team
Customer Focus: We win by knowing our customers
Requirements:
Bachelor's degree in Engineering or related field.
5+ years of experience in semiconductor reliability operations or process engineering.
Strong proficiency in MAM/MES systems, project management, and equipment planning.
Excellent communication and stakeholder management skills.
Experience with tactical planning and inventory management in a lab or manufacturing setting.
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Unlock Your Senior Engineer Potential: Insight & Career Growth Guide
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Great news! Micron is currently hiring and seeking a Senior Engineer – HIG PSE IE – Wafer Reliability Operation to join their team. Feel free to download the job details.
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An organization's rules and standards set how people should be treated in the office and how different situations should be handled. The work culture at Micron adheres to the cultural norms as outlined by Expertini.
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