Urgent! Senior Staff/Staff Design Verification Engineer Job Opening In Singapore, Singapore – Now Hiring Silicon Labs
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives.
Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications.
Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets.
Learn more at .**Meet the Team**
The IoT Digital team is a state-of-art IC design team focused on producing world-class Wireless MCU SoCs. The architecture specification, design, verification, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team.
These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, state-of-the-art power management, and best-in-class radios to support a wide range of wireless IoT applications and standards.As a Design Verification Engineer, you will be responsible for ensuring the correctness and functionality of complex digital designs, particularly those involving analog and mixed-signal components.
Your expertise in cosimulation will play a crucial role in verifying interactions between digital and analog blocks.
Below are the key responsibilities and qualifications for this role: **Duties & Responsibilities:*** Digital AMS Cosimulation:* Develop and maintain a cosimulation environment that allows seamless verification between digital RTL (Register Transfer Level) modules and analog/mixed-signal models (SV, Verilog A, VAMS, C/C++) or spices netlist.* Verify interactions, data exchange, and communication between these different representations of the design.* Testbench Development:* Create System Verilog-based VMM/UVM test benches for digital components.* Specify testbench requirements and coverage plans.* Implement constrained-random sequences, agents, and environments using UVM.* Complex Verification Environments:* Build and maintain complex and reusable verification environments using methodologies such as UVM and SystemVerilog (SV).* Write comprehensive test plans and create test benches to execute those plans.* Analyze coverage metrics, identify, and address test bench gaps, and run regressions.* File bug reports as needed.
**Qualifications:**Education: A relevant degree, such as a Master’s or Bachelor’s Degree in Computer Science, Electrical Engineering, Computer Engineering, or related fields.Skills:* Proficiency in System Verilog,
Assertion-based Formal Verification and UVM.* Familiarity with Verilog, Verilog A, C, and TCL* Knowledge of industry-standard interfaces.* Tools proficiency in Xcelium, Spectre, Questasim, Symphony* Scripting skills in languages like Python or Perl is a plus**Experience:**Ideally, 10-15 years of industry experience.**Benefits & Perks:**
*You can look forward to the following benefits:** Employee Stock Purchase Plan (ESPP)* Insurance plans with Outpatient cover* Flexible work policy#LI-Hybrid#LI-DK1*Silicon Labs is an equal opportunity employer and values the diversity of our employees.
Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.*At Silicon Labs, we hire and empower great talent to achieve their full potential.
By offering challenging projects, technical mentorship, and continuous learning opportunities, we ensure our employees thrive at every stage of their careers.
Here, you’ll work alongside some of the industry’s brightest minds, tackling complex problems that deepen your expertise and expand your horizons.
Whether you’re building new skills or shaping your career path, we’re dedicated to supporting your growth and celebrating your success every step of the way.
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Unlock Your Senior Staff Potential: Insight & Career Growth Guide
Real-time Senior Staff Jobs Trends in Singapore, Singapore (Graphical Representation)
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Great news! Silicon Labs is currently hiring and seeking a Senior Staff/Staff Design Verification Engineer to join their team. Feel free to download the job details.
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An organization's rules and standards set how people should be treated in the office and how different situations should be handled. The work culture at Silicon Labs adheres to the cultural norms as outlined by Expertini.
The fundamental ethical values are:The average salary range for a Senior Staff/Staff Design Verification Engineer Jobs Singapore varies, but the pay scale is rated "Standard" in Singapore. Salary levels may vary depending on your industry, experience, and skills. It's essential to research and negotiate effectively. We advise reading the full job specification before proceeding with the application to understand the salary package.
Key qualifications for Senior Staff/Staff Design Verification Engineer typically include Other General and a list of qualifications and expertise as mentioned in the job specification. Be sure to check the specific job listing for detailed requirements and qualifications.
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Before the Interview:To prepare for your Senior Staff/Staff Design Verification Engineer interview at Silicon Labs, research the company, understand the job requirements, and practice common interview questions.
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