Senior Role:
We are seeking a skilled Senior Engineer to join our team and contribute to the design and development of our advanced semiconductor products.
As a Senior Engineer, you will be responsible for the following:
Implementing off-chip memory built-in self-test (MBIST) and scan design techniques to enhance the testability and fault coverage of our designs.
Providing and maintaining Logical Equivalence Checking (LEC) and Synopsys Design Constraints (SDC) scripts for Formal Verification and Timing Constraint Check processes.
Collaborating with Test Engineers to analyze and understand Design-for-Testability (DFT) requirements and providing efficient solutions for DFT testing.
Requirements for Senior Role:
A Bachelor's or Master's degree in Electrical Engineering or a related engineering field.
Proficiency in programming skills and UNIX shell scripting.
Familiarity with Verilog and Register Transfer Level (RTL) design methodologies.
Manager Role:
We are looking for an experienced Manager to lead our team and oversee the successful execution of our semiconductor projects.
As a Manager, you will be responsible for the following:
Communicating with customers to understand their requirements and providing suitable test architecture planning for production.
Establishing effective communication channels with external teams to track issues and monitor progress related to our projects.
Managing project schedules and providing support to cross-functional engineering teams to ensure timely completion of tasks.
Assisting in the implementation of Design-for-Testability (DFT) structures and reviewing the work of team members.
Collaborating with test engineers to bring up test vectors on test-house/silicon platforms.
Requirements for Manager Role:
A Bachelor's or Master's degree in Electrical Engineering or a related engineering field.
Proficiency in programming skills and UNIX shell scripting.
Familiarity with Verilog, RTL, and Static Timing Analysis (STA) techniques.
Experience in compression/share code and Ultra Flow implementation.
Knowledge of MBIST/SCAN pattern build-up in Automatic Test Equipment (ATE) environments.