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Responsibilities
- Implement ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis).
- Define ISP hardware architecture based on product features, performance requirements, gate count, and power estimation.
- Verify logic at ISP and digital system levels.
- Optimize design for reduced gate count and low power consumption.
- Collaborate closely with the ISP Algorithm team on design activities.
Requirements
- Minimum MSEE, BSEE, or equivalent, with 3+ years of digital design and verification experience.
- Knowledge of CMOS Image Sensors and image signal processing (ISP).
- Experience with SystemC/C++, SystemVerilog, and Catapult HLS tool.
- Strong debugging and problem-solving skills.
- Good communication and interpersonal skills.
- Result-oriented with adaptable behavior.
Seniority level
Employment type
Job function
- Semiconductor Manufacturing
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