Description
Responsibilities
You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.
Specific responsibilities include:
The right candidate will be a self-starter who assumes full ownership of DV tasks and delivers high-quality results.
Develop test plans at block, sub-system, and chip level.
Execute SoC-based verification at full-chip.
Write C-based lib packages and tests.
Architect and implement scalable and reusable test benches using SystemVerilog and UVM.
Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.
Automating the test environment for randomized testing and scoreboarding.
Utilize advanced debugging techniques to identify and resolve design and verification issues.
Perform root-cause analysis and work with design teams to fix identified issues
Define and track functional and code coverage metrics to ensure thorough verification.
Ensure that verification quality meets or exceeds industry standards and project requirements.
Edge-based AI inference is preferred.
Requirements
Requirements
What you need to have to be successful
BSEE /MSEE 5-8 years Degree of experience in block, sub-system, and full-chip verification
Technologies: Experienced in ARM M/RISC-V (Preferred) SoC Verification, expert in AMBA AXI/AHB/APB, DMA, Flow Control, Serial Devices, Qo5, Low Power (CPF/UPF) Verification
Preferred technologies: DSP, Crypto, OTP, AI, Flash
Languages: Strong in SystemVerilog (UVM), Verilog, C/C++, Python, Perl or Makefile
Should have delivered multiple chips functioning to Specification.
Identify and manage verification deliverables, milestones, and schedules.
Proactively identify potential verification risks and develop mitigation strategies.
Collaborate with design, architecture, and software teams to understand and verify design intent.
Communicate verification progress, issues, and results to stakeholders and management.
Strong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges
Strong understanding/exposure to Design Verification for low-power battery-operated designs is highly desired.
C-based verification in an SoC environment is required
Experience with ARM processor-based designs and low-power design techniques is a plus.
The expectation is that the candidate will be required to maintain a regular in-office presence five days per week.
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