Staff Physical Design Engineer

Overview

Staff Physical Design Engineer at AMD.

This is a Physical Design Engineering role that will require taking the design from RTL to GDS with synthesis, Place and Route, timing, and Physical Verification.

Responsibilities

This engineer will work on high-speed multi-gigabit SerDes PHY designs.

This includes automated synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic applications, automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.

You will also support floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final sign-off for large IP delivery.

Qualifications

• Major in Electrical Engineering, Computer Science or related field; master’s degree with 6+ years or bachelor’s with 8+ years of working experience, preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs
• Proficiency in Python and/or Perl is required.
  
  Additional languages are a plus.
  
  
• Experience with scripts to automate design flow and quality checks.
  
  
• Experience in automated synthesis and timing-driven place and route of RTL blocks (Verilog preferred) for high-speed datapath and control logic applications.
  
  
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction; strong background in digital circuit techniques, robust implementation topologies for logic functions, and transistor-level circuit topologies for high-speed, low-power applications.
  
  
• Experience in floor planning, design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final sign-off for large IP delivery.
  
  
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation.
  
  

Academic Credentials

• Major in EE, CS or related; master’s degree preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs.
  
  

Location

Singapore

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.