Key Responsibilities
Perform
front-end digital IC verification
using
SystemVerilog and UVM methodology .
Collaborate with
system and software teams
on
FPGA-based verification and validation .
Lead
DFT activities
including Scan Insertion, ATPG, and Pattern Validation.
Work closely with the
test team
to debug and resolve production test issues.
Support
post-silicon functional debugging
for taped-out devices.
Participate in
design reviews , maintain ISO documentation, and ensure design process compliance.
Support continuous improvement in verification methodology and automation.
Requirements
Degree or Master’s in
Electrical / Electronic Engineering .
5+ years
of experience in
digital IC design verification
from design to tape-out.
Hands-on experience with
SystemVerilog, UVM/OVM , and
DFT/ATPG
methodologies.
Proficient in
EDA tools
(Cadence, Synopsys).
Knowledge in
digital/mixed-signal design ,
USB interfaces , and
connectivity technologies
(UART, SPI, I2C).
Strong analytical, debugging, and communication skills.
Able to work independently and in cross-functional teams.
For interested applicants, kindly send your resume in Word/PDF format to include the following in your resume including:
1.
Current Salary
2.
Expected Salary
3.
Availability
4.
Reason for leaving
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Magalit | R
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