Responsibilities
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To develop and maintain foundry PCM test pattern layout and description.
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To develop and run SVRF/Tcl scripts to generate layout pattern according to device truth table and design support manual
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To collaborate with design,integration lithography and MES team to facilitate mask making process
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To troubleshoot test pattern layout issue and optimize it
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To setup and calibrate TCAD deck file to provide device tuning and process optimization condition
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To maintain EDA software and user accounts
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Knowledge of Linux OS will be an adding advantage
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Experience of using EDA software Cadence layout, Synopsys Laker ,TCAD and Semens Calibre will be an adding advantage
Requirements
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Candidate must possess at least a Bachelor's Degree, Engineering(Electrical/Electronic) or equivalent.
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Semiconductor physics knowledge is must-be
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At least 2 years working experience in semiconductor foundry industry